The coprocessor0 in a MIPS processor has a set of registers

The coprocessor_0 in a MIPS processor has a set of registers used to store necessary information when an exception occurs: When a MIPS processor executes the following instructions: the contents of these registers in hexadecimal are:

Solution

BadVaddr ($8) stores the memory address at which the Exception occurs, In the above given instructions exception occured in store word instruction. hence

$8=6($t0)i.e., 0x00404006 . On comparing a=0x00404006

Cause ($13) defines the type of exception and pending interrupt bits if any and here storing of word leads to the exception ExcCode will be 5 and since IP bits are 0 (8-15) bits in Cause will be

$13=0x00000005 On comparing b=0x00000005

EPC($14) stores the address of instruction that caused the exception and here

$14= 0x00404004 on comparing c=0x00404004