Follow the Verilog 2001 standard write the Verilog code for

Follow the Verilog 2001 standard write the Verilog code for 8-3 priority encoder using for loop.

Solution

module encoder (
input wire [7:0] in,
output reg [2:0] out
);

genvar i; //a generate block needs a genvar

generate
    for (i=0;i<7;i=i+1) begin :gen_block
      always @* begin
        if (in[i]==1\'b1 && in[7:i+1]==\'b0)
          out = i;
        else
          out = 3\'bZZZ;
      end
    end
endgenerate

always @* begin

    if (in[7])
      out = 3\'d7;
    else
      out = 3\'bZZZ;
end
endmodule