Consider the following code segment LD R1 0R2 SUB R4 R1 R5 A

Consider the following code segment: LD R1, 0(R2) SUB R4, R1, R5 AND R6, R1, R4 OR R8, R4, R6 List all potential dependencies & data hazards that exist (for our 5 stage pipeline). Remember that a dependency may exist that is not a hazard on your particular pipeline. Assume that your CPU cannot forward. Without changing the order of instructions show how the minimal number of NOPS can be inserted between the instructions to eliminate the hazards. Assume that your CPU can forward. Now show the minimal number of NOPS that must be inserted to eliminate the hazards.

Solution

As data hazard occurs when an instruction depends on the result of a previous instruction in a way that it leads to the overlapping of instructions in the pipeline. It is of 3 types-

The 5 stages in instruction pipeline are-

Let us say there are 4 instructions namely I1, I2, I3 and I4

I1: LD R1,0(R2) - Load R1 from address 0 + R2 -- It will pass all 5 stages

I2: SUB R4,R1,R5 - Perform R1-R5 and Store it in R4 -- It also uses WB

I3: AND R6,R1,R4 - Perform R1 AND R4 and Store it in R6 -- I2 is calculating a value to be saved in register R4, and I3 is going to use R4 to compute a result for register R6. However, in a pipeline, when operands are fetched for the 2nd operation, the results from the first will not yet have been saved, and hence a data dependency occurs.

As I3 is dependent on the completion of instruction I2 hence data dependency occurs with I3 due to RAW.

I4: OR R8,R4,R6 - Perform R4 OR R6 and Store it in R8 -- In the same wayR4 and R6 are used to calculate a value to be stored in R8. I4 is data dependent on I3 by RAW.