Homework SourseCreate the dataflow and behavioral vhdl for the Logic Extend
Solution
The dataflow vhdl for Logic Extender:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY logicExtender IS
PORT( ai : IN STD_LOGIC;
bi : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
xi : OUT STD_LOGIC);
END logicExtender;
ARCHITECTURE dataflow OF logicExtender IS
BEGIN
xi <= (s(2) AND ai) OR
(NOT s(0) AND ai) OR
(NOT s(1) AND ai AND bi) OR
(NOT ai AND (s(0) OR bi) AND s(1) NOT s(2));
END dataflow;
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The behavioral VHDL for Logic Extender is:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY logicextender IS
PORT( ai : IN STD_LOGIC;
bi : IN STD_LOGIC;
s : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
xi : OUT STD_LOGIC);
END logicextender;
ARCHITECTURE behavior OF logicextender IS
BEGIN
PROCESS (s, ai, bi)
BEGIN
IF ai = \'0\' THEN
CASE s IS
WHEN \"010\" => xi <= bi;
WHEN \"011\" => xi <= \'1\';
WHEN OTHERS => xi <= \'0\';
END CASE;
ELSE
CASE s IS
WHEN \"001\" => xi <= bi;
WHEN \"011\" => xi <= \'0\';
WHEN OTHERS => xi <= \'1\';
END CASE;
END IF;
END PROCESS;
END behavior;
