module halfadderabsco input ab output sco wire an bn n1 n2 n

module half_adder(a,b,s,co);
input a,b;
output s,co;
wire an, bn, n1, n2;

not b1 (an,a);
not b2 (bn,b);
and b3 (n1, an, b);
and b4 (n2, bn, a);
or b5 (s, n1,n2);
and b6 (co, a,b);

endmodule

Create a test fixture and run simulation using Cadence Verilog XL. plz

Create a test fixture and run simulation using Cadence Verilog XL. Plz

Step1:In setup environment dialog box initialize a simulation run directory

With name had.run1

Observe initial Verilog-XL simulation control window.

Observe The Record Signals dialog box

Step2: create a new testfixture template in dialog by clicking yes.

Observe Verilog-xL stimulus Options form with file name textfixture.verilog

Step3:find the Testfixture for the half adder. Do not create a module in this file.