For the following lab assignment you will write VHDL code AN

Solution

4 to 2 priority Encoder

VHDL PROGRAM ::::

- Circuit : Four Input Priority Encoder
--
-- Structure:
--
-- The Priority Encoder can be designed with five
-- OR gates, one AND gate, one Inverter. Such realization
-- of the circuit is shown on Teahlab.com. The circuit is
-- interactive; so you may verify it.
--
-- Teahlab takes a structural approach to the VHDL design
-- of the Priority Encoder. Hence, we design the circuit
-- in two stages:
--
-- In stage one we define three basic entities:
-- AND, OR, NOT.
-- In stage two we use the basic entities to construct
-- the encoder.                  
--
-- One of the advantages of structural designs is that
-- from the VHDL program you can tell what the physical
-- circuit looks like.
--
-- It is very important to learn structural design (RTL)
-- strategies because as your assignments become larger
-- and larger, knowledge of register transfer level (RTL)
-- design strategies become indispensable.
-------------------------------------------------------------

-- This is the AND gate
library ieee;
use ieee.std_logic_1164.all;

entity andGate is
port( A, B : in std_logic;
F : out std_logic);
end andGate;

architecture func of andGate is
begin
F <= A and B;
end func;
--*============================
-- This is the OR gate
library ieee;
use ieee.std_logic_1164.all;

entity orGate is
port(   A, B : in std_logic;
F : out std_logic);
end orGate;

architecture func of orGate is
begin
F <= A or B;
end func;
--*============================
-- This is the NOT gate
library ieee;
use ieee.std_logic_1164.all;

entity notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end notGate;
--
architecture func of notGate is
begin
outPort <= not inPort;
end func;
--*=====================*====================

--Now we write the RTL definition for the Priority Encoder
library ieee;
use ieee.std_logic_1164.all;

entity Priority_Encoder is
port( D3, D2, D1, D0 : in std_logic;
A1, A0, V : out std_logic);
end Priority_Encoder;
--
architecture Func of Priority_Encoder is

component andGate is --import AND Gate entity
port( A, B : in std_logic;
F : out std_logic);
end component;

component orGate is --import OR Gate entity
port( A, B : in std_logic;
F : out std_logic);
end component;

component notGate is --import NOT Gate entity
port( inPort : in std_logic;
outPort : out std_logic);
end component;

signal andOut, orOut1, orOut2, invOut: std_logic;

begin
-- Just like the real circuit,
-- there are four components: G1 to G4
G1: notGate port map(D2, invOut);
G2: andGate port map(invOut, D1, andOut);
G3: orGate port map(D3, D2, orOut1);
G4: orGate port map(D1, D0, orOut2);

OUT_1: orGate port map(D3, andOut, A0); -- A0
OUT_2: orGate port map(D3, D2, A1); -- A1
OUT_3: orGate port map(orOut1, orOut2, V); -- V

end Func;
----------------------------------------------------------END
----------------------------------------------------------END

TEST BENCH :::

Program: Four Input Priority Encoder Testbench
--
-- Note : A testbench is a program that defines a series
-- of tests to verify the operation of a circuit.
--
-- Two important notes about this test bench:
-- 1] The testbench takes no inputs and returns
-- no outputs. As such the ENTITY declaration
-- is empty.
--
-- 2] The circuit under verification, here the
-- Encoder, is imported into the testbench
-- ARCHITECTURE as a component.
-------------------------------------------------------------

--import std_logic from the IEEE library
library ieee;
use ieee.std_logic_1164.all;

entity Priority_Encoder_tb is
end Priority_Encoder_tb;

architecture tb of Priority_Encoder_tb is

component Priority_Encoder is
port( D3, D2, D1, D0 : in std_logic;
A1, A0, V : out std_logic);
end component;

signal D3, D2, D1, D0, A1, A0, V : std_logic;

begin
mapping: Priority_Encoder
port map(D3, D2, D1, D0, A1, A0, V);

process
variable errCnt : integer := 0;
begin
--The \"assert\" keyword allows you to test certain
--conditions. In other words, the point of assertion is
--to allow you to inspect what you expect.
  
--TEST 1
D3 <= \'0\';
D2 <= \'1\';
D1 <= \'0\';
D0 <= \'1\';
wait for 15 ns;
assert(A1 = \'1\') report \"Error 1\" severity error;
assert(A0 = \'0\') report \"Error 1\" severity error;
assert(V = \'1\') report \"Error 1\" severity error;
if(A1 /= \'1\' or A0 /= \'0\' or V /= \'1\') then
errCnt := errCnt + 1;
end if;
  
--TEST 2
D3 <= \'1\';
D2 <= \'0\';
D1 <= \'1\';
D0 <= \'0\';
wait for 15 ns;
assert(A1 = \'1\') report \"Error 1\" severity error;
assert(A0 = \'1\') report \"Error 1\" severity error;
assert(V = \'1\') report \"Error 1\" severity error;
if(A1 /= \'1\' or A0 /= \'1\' or V /= \'1\') then
errCnt := errCnt + 1;
end if;

--TEST 3
D3 <= \'0\';
D2 <= \'0\';
D1 <= \'0\';
D0 <= \'0\';
wait for 15 ns;
assert(A1 = \'0\') report \"Error 1\" severity error;
assert(A0 = \'0\') report \"Error 1\" severity error;
assert(V = \'0\') report \"Error 1\" severity error;
if(A1 /= \'0\' or A0 /= \'0\' or V /= \'0\') then
errCnt := errCnt + 1;
end if;
------------SUMMARY---------------------
if(errCnt = 0) then
assert false report \"Success!\" severity note;
else
assert false report \"Faillure!\" severity note;
end if;

end process;
end tb;
-------------------------------------------------------------
configuration cfg_tb of Priority_Encoder_tb is
for tb
end for;
end cfg_tb;
----------------------------------------------------------END
----------------------------------------------------------END