create and test a D latch Create and test a D latch Create a

Create and test a D latch Create a new Quartus II project and write a Venlog HDL code using the style of code in Figure I for the gated D latch (Figure 2). Compile the code Verify that the latch works properly for all input conditions by using functional simulation Examine the timing characteristics of the circuit by using timing simulation

Solution

A Latch has 2 stable states and can be used to store state info. D s actually a delay line.

D latch:

module dff_from_nand();
wire Q,Q_BAR;
reg D,CLK;

nand N1 (S_g,S,CLK) ;
nand N2 (R_g,R,CLK) ;
nand N3 (Qa,Qb,S_g);
nand N4 (Qb,Qa,Rg);

initial begin
$monitor(\"CLK = %b D = %b Qa = %b Qb = %b\",CLK, D, Qa, Qb);
CLK = 0;
D = 0;
   D = 1;
D = 0;
$finish;
end  

always CLK = ~CLK;

endmodule

// considered S=D and R=~D for the program.

Thanks