It is required to connect memory to a digital system such th
Solution
Solution:
The address map of ram and Rom chips involves two steps.
step1:
Firstly combine 2K x 8ROM into 2k X 32 ROM . It as to be connected in parallel and the input address are common. . The data outputs are kept separate to for the 32 lines required. The chips are enable and a read line are active low.
step2:
In this step it involves combining four \"2k x 32 bit\" ROM units. The input ADDRESS LINES (A0 - A10) and output address are also connected together in parallel. This just leaves the problem of the CONTROL LINES. The read line is commoned to ROM to output the data with a single \'read\' signal. The chip is enabled are used as an extra address signal to ensure that only ONE 2k x 32 bit block is addressed at any given time. The input addresses A11 and A12 to give the full 8K address for the ROM and add a 2 to 4 line decoder to convert these address lines to CHIP ENABLE selections.
