Write a procedure that logs the history of values of a bitve

Write a procedure that logs the history of values of a bit-vector signal to a text file.

Each time the signal changes, write the current time and signal value to the file.VHDL

has a built in function called NOW that returns the current simulation time when it is

called.

Solution

Solution:

procedure of a bit-vector signal :

procedure WRITE(L : inout LINE; VALUE : in integer; JUSTIFIED: in SIDE := right; FIELD: in WIDTH := 0);

signal o_valid : std_logic;
signal o_add : std_logic_vector(7 downto 0);
p_dump : process(i_rstb,i_clk)
file test_vector : text open write_mode is \"output_file.txt\";
variable row : line;
begin
  
if(i_rstb=\'0\') then
------------------------------------
elsif(rising_edge(i_clk)) then
  
if(o_valid = \'1\') then
  
write(row,o_add, right, 15);
  
write(row,conv_integer(o_add), right, 15);
hwrite(row,o_add, right, 15);
hwrite(row,\"00000000\"&o_add, right, 15);
  
writeline(test_vector,row);
  
end if;
end if;
end process p_dump;

==>VHDL has a built in function called NOW that returns the current simulation time when it is called a Testbench.

>> A simulation program is used to test the logic design using simulation models to represent the logic circuits that interface to the design. This collection of simulation models is commonly called a Testbench.