Processor Architecture Suppose there are no conditional bran

(Processor Architecture) Suppose there are no conditional branch other than the one at L1 , at least how many pairs of predicate registers is needed?

N1. One way of dealing with branch instructions is to use the concept of predicated instruction. For example, each instruction is tagged with 1-bit condition, and then processor executes the instruction only if the condition tag is l (true). Consider a predicated instruction with a pair of 1-bit predicate registers pT and pF (pT) ADD RO, RO, R4 which RO RO+R4 if (pT) 1, 1.e. True. Otherwise, the ADD instruction behaves as would a NOP instruction Let\'s assume there\'s a new instruction setting the predicate registers: CMP EQ p T, p R1, R2 which means 1-bit value of the predicate registers pT and pF will be assigned as a result of comparing R1 and R2 to pT (R1 R2) and p F (R1 R2). For the code structure shown below, answer the questions: L1 if then 1... L2 else f...... L3 L4

Solution

we need three pairs of predicate registers

1.the first pair to store registers R0 AND R1

2.The second pair to store R1 AND R2

3.The third pair for register R4 AND ANY ONE OF THE REGISTERS(R0,R1,R2))