Write a VHDL function that converts a 5bit bitvector to an i

Write a VHDL function that converts a 5-bit bit_vector to an integer. Note that the integer value of the binary number a_4a_3a_2a_1a_0 can be computed as ((((0 + a_4)*2 + a_3)*2 + a2)*2 + a_1)*2 + a_0 How much simulated time will it take for your function to execute?

Solution

is \'std_logic_vector\' signed data or unsigned data? Signed data means that your std_logic_vector can be a positive or negative number. Unsigned data means that your std_logic_vector is only a positive. when converting std_logic_vector to integer, you have to convert to signed or unsigned before to clarify the sign