Consider the 5stage RISC pipeline that we discussed in the c

Consider the 5-stage RISC pipeline that we discussed in the class. In an attempt to improve it, a student splits Mem stage into MemR (memory read) and MemW (memory write) stage. So, now the order of stages is IF, ID, EX, MemR, MemW, and WB. At any clock cycle, data memory can be accessed by at most one of the memory stages. A branch instruction is resolved in EX stage. Lets assume that of all instructions, 30% are loads, 20% are stores, 10% are branches and the rest are other type of instructions (ALU instructions). For any ALU and load instruction i, there is a probability of 15%, 10%, 5% and, 3% that instruction i+1, i+2, i+3 and i+4 will depend on it respectively. When instruction i+1 depends on instruction i, no later instructions (i+2, i+3, ...) depend on i. The same is true for i+2, i+3 etc. In all cases, there is a 10% chance that the dependent instruction is a store operation with dependence only on register rt. For any store instruction i, there is a probability of 10% that instruction i+1 is a load instruction. Assume full forwarding support. Now calculate the following quantities: a) Maximum and average number of stall cycles due to a load instruction b) Maximum and average number of stall cycles due to a store instruction c) Maximum and average number of stall cycles due to an ALU instruction d) Maximum and average number of stall cycles due to a branch instruction e) What is the CPI? f) If clock rate is 1 GHz, what is the MIPS rating?

Solution

there are 5 kinds of instructions for the multi-cycle MIPS:

Load - 5 cycles

Store - 4 cycles

R-type - 4 cycles

Branch - 3 cycles

Jump - 3 cycles

CPI = (0.3*5+0.2*4+0.1*1+3.3*4)/3.9

= (1.5+0.8+0.1+13.2)/3.9=4