65536 words main memory sytem of block size of 4 words makin

65536 words main memory. sytem of block size of 4 words making 2k lines.

a. calculate number of addressable bits

B number of blocks

c. line size

D. a cache of 16 MB needs to be organized into how many liines for direct main memory mapping in above question.

Solution

65536 words main memory. sytem of block size of 4 words making 2k lines.

a. calculate number of addressable bits

B number of blocks

c. line size

D. a cache of 16 MB needs to be organized into how many liines for direct main memory mapping

Answer:-

a. calculate number of addressable bits .

1. Word = typically size of int, 32 bits now.

2. Addressable units: usually bytes, but can be words. 2A = number of addressable units, where A is bits in an address.

3. Unit of transfer = number of bits written out or read in to memory at a time. On Pentium, 64-bits

B. number of blocks

1. Memory block = unit of main memory stored in a cache line.

2. Cache line = basic unit of a cache that contains a block of memory, a tag, and the control bits used to determine when the line should be replaced.

3. Cache tag = a number stored in a line that is combined with the line’s position in the cache to determine the address of the line’s block in main memory.

4. Cache hit = when the data for a CPU specified address is in a cache.

5. Cache miss = when the data for a CPU specified address is not in a cache. This will force some line in the cache to be replaced with the desired data.

6. Dirty = when a line contains updated data that differs from the corresponding main memory. Before overwriting, this data must be copied back to the main memory.

c. line size

1)The line index will be the LSBs of the block number, and the tag will be MSBs of the block number.

2)For our example, tag length = 17 – 4 = 13 bits = number of bits remaining to be specified when we utilize the 4-bit line index as the LSBs of the block number.

D. a cache of 16 MB needs to be organized into how many liines for direct main memory mapping

1. The data cache is 16 Kbytes, with a line size of 64 bytes, and a four-way set associative organization. Uses write-back policy. Has an instruction that writes back and invalidates the caches for context switches.

2. The instruction cache between instruction decode logic and the execution core because the microcode is more uniform, and isolates the cache from the slow decoding of the CISC to RISC.