For a singlecycle processor assume the following latencies f

For a single-cycle processor, assume the following latencies for logic blocks in the datapath: what is the clock cycle time if the only type instructions we need to support are ALU instructions (i.e., add, and, ...etc)? what is the clock cycle time if we only had to support !w instructions? what is the clock cycle time if we must support add, beq, lw, and sw instructions? For the remaining problems, assume that we use the above logic blocks in another pipelined processor. Also, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: In what fraction of all cycles is the data memory used? (496) If we can improve the latency of one of the given datapath components by 20%, which component should it be to optimize the overall performance? what is the speed-up from this improvement?

Solution

Since Mux value is not given, I have assumed the clock time for Mux to be 0.

(a)
Path for ALU instructions: I-Mem, Regs, Mux, ALU, Mux, Regs
   500 + 220 + 180 + 220 = 1120(ps)
  
For parallel processing of I-Mem and Regs(Write-Back): I-Mem, Regs, ALU
   500 + 220 + 180 = 900(ps)

(b)
Path for ALU instructions: I-Mem, Regs, Mux, ALU, D-Mem, Mux, Regs
   500 + 220 + 180 + 1000 + 220 = 2120(ps)

For parallel processing of I-Mem and Regs(Write-Back): I-Mem, Regs, Mux, ALU, D-Mem, Mux
   500 + 220 + 180 + 1000 = 1900(ps)
     
(c)
Same as in part (b) since lw instruction has critical path.

(d)
Since, the lw and sw instructions use the data memory =>
   35% + 15% = 50%