The core of the microcontroller ST32F407 is a a 16bit RISC p

The core of the microcontroller ST32F407 is a. a 16-bit RISC processor. b. a 32-bit RISC processor. c. a 32-bit CISC processor. The architecture of the microcontroller ST32F407 is a. \"Von Neumann\" architecture. b. \"Harvard\'\' architecture. c. Neither \"Von Neumann\" nor \"Harvard\" architecture. The function which is not supported by an assembly instruction of M4 processor is a Square root

Solution

Answers:

1. (b). a 32-bit RISC architecture.

2. (b). harvard architecture.

Description:

These are the definition and basic facts about this ST32F407 microcontroller. It is a 32-bit RISC architecture having frequency up to 168 MHz for operation.

It is following the harvard architecture because it is having separate instruction bus and the data bus. That means when the CPU is doing the work of fetching the next instruction, another read/write operation can be done parallel without affecting CPU operations.