Write a Verilog module using a casex statement that takes a

Write a Verilog module using a casex statement that takes a 4-bit value as input and outputs the number of leading 1’s, e.g., 0111 -> 0, 1011 -> 1, 1100 -> 2, etc.

Solution

module priory_encoder_case
(
input wire [4:1] x,
output reg [2:0] pcode
);
always @ *

case (x)
4\'b1000, 4\'b1001 , 4\'b1010, 4\'b1011 , 4\'b1100 , 4\'b1101, 4\'b1110 , 4\'b1111 :
pcode = 3\'b100;
4\'b0100, 4\'b0101 , 4\'b0110, 4\'b0111 :
pcode = 3\'b011 ;
4\'b0010, 4\'b0011 :
pcode = 3\'b010;
4\'b0001 :
pcode = 3\'b001;
4\'b0000 :
pcode = 3\'b000;
endcase

endmodule  


Note that the forever statement forever @(x[4], x[3],x[2], x[1]) might be written as forever @ * we tend to currently recommend that you just write a take a look at bench for this code and verify that it works. If you\'ve got sifficulty, you\'ll be able to check it with following take a look at bench


`timescale 1ns / 1ps
module stimulus;
   reg [4:1] x;
   wire [2:0] pcode;
   // Instantiate the Unit underneath take a look at (UUT)
   priory_encoder_case uut (
       .x(x),
       .pcode(pcode)
   );

   initial begin
       // Initialize Inputs
x = 4\'b0000;   

   #20 x = 4\'b0001;
   #20 x = 4\'b0010;
   #20 x = 4\'b0011;
   #20 x = 4\'b0100;
   #20 x = 4\'b0101;
   #20 x = 4\'b0110;
   #20 x = 4\'b0111;
   #20 x = 4\'b1000;
   #20 x = 4\'b1001;
   #20 x = 4\'b1010;
   #20 x = 4\'b1011;
   #20 x = 4\'b1100;
   #20 x = 4\'b1101;
   #20 x = 4\'b1110;
   #20 x = 4\'b1111;
   #40 ;

   end

       initial begin
       $monitor(\"t=%3d x=%4b,pcode=%3b\",$time,x,pcode );
       end

endmodule


Notice the utilization of the case statement
4\'b1000, 4\'b1001 , 4\'b1010, 4\'b1011 , 4\'b1100 , 4\'b1101, 4\'b1110 , 4\'b1111 :
pcode = 3\'b100;


When the valley of x matches any of the subsequent values
4\'b1000, 4\'b1001 , 4\'b1010, 4\'b1011 , 4\'b1100 , 4\'b1101, 4\'b1110 , 4\'b1111 :
The statement next thereto
pcode = 3\'b100;
is dead. Notice that this might even be are written as
4\'b1000, 4\'b1001 , 4\'b1010, 4\'b1011 , 4\'b1100 , 4\'b1101, 4\'b1110 , 4\'b1111 :
begin
pcode = 3\'b100;
end

Write a Verilog module using a casex statement that takes a 4-bit value as input and outputs the number of leading 1’s, e.g., 0111 -> 0, 1011 -> 1, 1100 -
Write a Verilog module using a casex statement that takes a 4-bit value as input and outputs the number of leading 1’s, e.g., 0111 -> 0, 1011 -> 1, 1100 -

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