What are the different modeling styles in VHDL Give the synt

What are the different modeling styles in VHDL? Give the syntax for entity Give the syntax for architecture What is the difference between entity and architecture? What is the difference between the schematic generated on RTL analysis and schematic generated after synthesis? How do you set the run time for simulation? What does FPGA stand for?

Solution

4.) VHDL stands for VHSIC Hardware Description Language.

Modeling Style is a means to how we Design our Digital IC\'s in Electronics. With the help of modeling style we describe the Design of our Electronics.

There are basically 3 modelling styles primarily used in VHDL:

Data Flow Modelling Style: Data Flow Modeling Style Shows that how the data / signal flows from input to ouput threw the registers / Components.

Structural Modelling Style: Structural Modeling Style shows the Graphical Representation of modules/ instances / components with their Interconnection.

Behavior Modelling Style: Behavior Modeling Style shows that how our system performs according to current input values.

5.) Entity: Entity is the description of the interface between a design and its external environment.

This is the simplified syntax of entity in VHDL:

entity entity_name is

      generic (generic_list);

      port (port_list);]

end entity entity_name;

6.) Architecture: A body associated with an entity declaration to describe the internal organization or operation of a design entity.

This is the simplified syntax of architecture in VHDL:

architecture architecture_name of entity_name is

  architecture_declarations

begin

  concurrent_statements

end [ architecture ] [ architecture_name ];

7.) Architecture is a part of entity that decribes the operation of entity