HW2 Task3 RTL programing Simplified CPU architecture SPEC AL

HW2: Task-3 RTL programing Simplified CPU architecture SPEC: ALU Define your own instruction format (32bits) OP: operation code. (at least 3 bits) Register bank RS1: source register-1 RS2: source ALU RD: destination register Plan your own memory Memory MISC: other bits for extension purpose. address partiti Instructions: (minimum requirement: 8) DON\'T copy-paste from ECE4150 (which is structure level of coding). We do behavior coding here! CPU vs. Instruction memory CPU vs. Register Bank Sample Instruction: add $s0, $s1, $s2 CPU MEMORY 255 REG 1\'s REG 1\'s value 32, REG 2\'s REG 2\'s (RD) WRITE REG 10000 DATA TO WRITE Control Sig. Write Sig. 3 0 0 0 0 0 0 1 0 2 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 7 6 5 4 3 2 1 0 Let\'s load our program into memory: add $50 $s2 Data (8-bit wide 1 byte) 00000010 00110010 10000000 00100000

Solution

To keep this as easy as moderately doable, we tend to think about an easy instruction format within which each instruction is entirely depicted in one word. That is, the word is split into fields like \"opcode\", \"register number\", and \"memory address\", that area unit forever identical for all directions, quite in contrast to the PDP-11 case. what is more, the memory address seems directly within the instruction word, not during a subsequent word (perhaps the words area unit wider than sixteen bits).

Here may be a easy one-bus design we\'ll use for many of our examples during this course. knowledge ways depicted by the big arrows (namely, every arrow to or from the bus aside from the ALU input, and Zin) correspond to microprogram management lines.

Control lines additionally embrace browse and Write (memory functions), Wait MFC, the ALU functions, Set CC, Set Carry-In, carry-over, Zero A, Complement B, and End.

Set CC causes the condition codes to be set by this ALU operation. That is, it is the water level for the condition code register.

Carry-Forward causes the C condition code to be equipped as Carry-In (i.e. the perform from a previous ALU operation is equipped because the carry in to the new ALU operation). Set Carry-In provides associate unconditional \'1\' as Carry-In.

\"Zero A\" provides a zero price to the ALU which might be employed in identical cycle, while not moving the contents of Y. That is, Zero A overrides the Y output with a zero price.

\"Complement B\" flips all of the bits within the \'B\' ALU input (the one from the bus). This helps with two\'s-complement subtraction (which sometimes then additionally uses Set Carry-In to feature one).

End makes this microinstruction the last microinstruction of the microroutine by resetting the µPC.

There also are eight conditional microbranch management lines, of the shape \"If C then End\", \"If C\' then End\", so on for all of C, V, Z, and N. ALU operations solely set the condition codes if the Set CC bit is on (else we tend to could not implement branch directions with associate offset while not ruin the condition codes!). Note that once a microbranch is taken, this microinstruction still completes, even as it will with the top management line.