Homework SourseAssume that each of PG Unite Carry Look ahead CLA Unit and S
Assume that each of PG Unite, Carry Look ahead (CLA) Unit and Sum unit has a delay of 2delta, what will be the Delay of:
1- 128-bit adder if for design complexity reasons, the size of each CLA is limited to 4-bits.
2- 256 -bit adder if for design complexity reasons, the size of each CLA is limited to 8-bits.
Show one equation that represent each level of dealy, example PG unit, first level CLA ( show C0) etc.
Solution
Ca rry look
-
a he a d a dde r
As seen in th
e ripple
-
carry adder, its
limitin
g factor
is the time it takes to propagate the carry.
The carry look
-
ahead adder solves this problem by calculating the carry signals in advance,
based on the input
signals. The result is a reduced carry propagation time.
To be able to understand how the carry look
-
ahead adder wo
rks, we have to manipulate the
B
oolean expression dealing with the full ad
der. The Propagate P and generate G in a full
-
adder,
is given as
:
P
i
= A
i
B
i
Carry propagate
G
i
= A
i
B
i
Carry generate
Notice that both pro
pagate and generate signals
depend
only
on the input bits and thus will be
valid after one gate delay.
The new expressions for the output sum and the carryout are given by
:
S
i
= P
i
C
i
-
1
C
i+1
= G
i
+ P
i
C
i
These equations show that a carry signal will be generated in two cases:
1) if both bits A
i
and B
i
are 1
2) if either A
i
or B
i
is 1 and the carry
-
in C
i
is 1.
Let\'s apply these equations for a 4
-
bit adder:
13
C
1
= G
0
+ P
0
C
0
C
2
= G
1
+ P
1
C
1
= G
1
+ P
1
(G
0
+ P
0
C
0
) = G
1
+ P
1
G
0
+ P
1
P
0
C
0
C
3
= G
2
+ P
2
C
2
= G
2
+ P
2
G
1
+ P
2
P
1
G
0
+ P
2
P
1
P
0
C
0
C
4
= G
3
+ P
3
C
3
= G
3
+ P
3
G
2
+ P
3
P
2
G
1
+ P
3
P
2
P
1
G
0
+ P
3
P
2
P
1
P
0
C
0
These expressions show that C2, C3 and C4 do not depend on its previous carry
-
in. There
fore
C
4
does not need to wait for C
3
to propagate. As soon as C
0
is computed, C
4
can reach steady
state. The same is also true for C
2
and C
3
The general expression is
C
i+1
= Gi
+
PiG
i
-
1
+ PiP
i
-
1
G
i
-
2
+ ....... P
i
P
i
-
1
....P
2
P
1
G
0
+ PiP
i
-
1
....P
1
P
0
C
0
.
This
is
a two
level Circuit. In CMOS however the delay of the function is nonlinerly dependent
on its fan in. Therefore large fanin gates are not practical.
Carry look
-
ahead adder’s structure can be divided into three parts: the propagate
