Problem 2 125 pts Consider the internal structure of the pse

Problem #2 125 pts] Consider the internal structure of the pseudo-CPU discussed in class augmented with a single-port register file i.e., only one register value can be read at a time) containing 32 8-bit registers (RO-R31). Suppose the pseudo-CPU can be used to implement the AVR instruction ST -x, R3. Give the sequence of microoperations required to Fetch and Execute AVR\'s ST -x, R3 instruction. Your solutions should result in exactly 6 cycles for the fetch cycle and 7 cycles for the execute cycle. You may assume only the AC and PC registers have the capability to increment/decrement itself. Assume MDR register is 8-bit wide (which implies that memory is organized into consecutive addressable bytes), and AC, PC, IR, and MAR are 16-bit wide. Also, assume Internal Data Bus is 16-bit wide and thus can handle 8-bit or 16-bit (as well as portion of 8-bit or 16-bit transfers in one microoperation. Clearly state any other assumptions made.

Solution

The data location is pointed to by the X (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes.
To access another data segment in devices with more than 64K bytes data space, the RAMPX, RAMPY, RAMPZ in register in the I/O area has to be changed.
The X pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented.
For fetch opertion:

clr R3;
ldi R2,$60 ; Set X low byte to $60
clr R8;
ldi R7,$60 ; Set X low byte to $60
ldi X,R8;
clr R9;

For Exceute Cycles:

MOV R9, #1;
ADD R9,R8,#1;
CMP R9, R8 ; Check whether value updated
STREQ R9, [SP]   
STRNE R9, [R3, #4] ;   
LRD R3, [R7];
BL free