Homework SourseEET 842 Lab Binarytosevensegment converter Create a new proj
EET 842 Lab Binary-to-seven-segment converter
Create a new project in a new directory for this assignment. If you are using the lab computers in W214,
log in using your GUS id and password.
Use a single VHDL program for this assignment. Note that when you use a single VHDL program, the
entity name you use in your VHDL program must match the filename of your .vhd file and the top-level
design entity you declare in when you create the project. Do not use spaces or symbols or start with a
number for the filename or directory as the simulator can not handle them.
Write a VHDL program for the DE0 using a selected signal assignment statement to do the following:
The input will be a four-bit binary number. Use SW3, SW2, SW1, and SW0 for the input. SW3 will be the
most significant bit while SW0 will be the least significant bit. Your program should display the
equivalent hexadecimal number on the seven-segment LED display HEX0. For example, an input of 1100
will display C (segments 3, 4, 5, and 0 on) and an input of 1000 will display 8 (all segments on). Refer to
the DE0 User Manual for information on how the seven-segment display is connected. Note that the
seven-segment displays are connected such that a 0 will turn a segment on and a 1 will turn it off.
Perform a functional simulation testing all possible inputs for your program. After verifying that your
program will work correctly, program the DE0 board with your VHDL program.
Upload the following files:
Your .qpf file
Your .vhd file
Your .qsf file
Your .vwf file
EET 842 Lab Binary-to-seven-segment converter
Create a new project in a new directory for this assignment. If you are using the lab computers in W214,
log in using your GUS id and password.
Use a single VHDL program for this assignment. Note that when you use a single VHDL program, the
entity name you use in your VHDL program must match the filename of your .vhd file and the top-level
design entity you declare in when you create the project. Do not use spaces or symbols or start with a
number for the filename or directory as the simulator can not handle them.
Write a VHDL program for the DE0 using a selected signal assignment statement to do the following:
The input will be a four-bit binary number. Use SW3, SW2, SW1, and SW0 for the input. SW3 will be the
most significant bit while SW0 will be the least significant bit. Your program should display the
equivalent hexadecimal number on the seven-segment LED display HEX0. For example, an input of 1100
will display C (segments 3, 4, 5, and 0 on) and an input of 1000 will display 8 (all segments on). Refer to
the DE0 User Manual for information on how the seven-segment display is connected. Note that the
seven-segment displays are connected such that a 0 will turn a segment on and a 1 will turn it off.
Perform a functional simulation testing all possible inputs for your program. After verifying that your
program will work correctly, program the DE0 board with your VHDL program.
Upload the following files:
Your .qpf file
Your .vhd file
Your .qsf file
Your .vwf file
EET 842 Lab Binary-to-seven-segment converter
Create a new project in a new directory for this assignment. If you are using the lab computers in W214,
log in using your GUS id and password.
Use a single VHDL program for this assignment. Note that when you use a single VHDL program, the
entity name you use in your VHDL program must match the filename of your .vhd file and the top-level
design entity you declare in when you create the project. Do not use spaces or symbols or start with a
number for the filename or directory as the simulator can not handle them.
Write a VHDL program for the DE0 using a selected signal assignment statement to do the following:
The input will be a four-bit binary number. Use SW3, SW2, SW1, and SW0 for the input. SW3 will be the
most significant bit while SW0 will be the least significant bit. Your program should display the
equivalent hexadecimal number on the seven-segment LED display HEX0. For example, an input of 1100
will display C (segments 3, 4, 5, and 0 on) and an input of 1000 will display 8 (all segments on). Refer to
the DE0 User Manual for information on how the seven-segment display is connected. Note that the
seven-segment displays are connected such that a 0 will turn a segment on and a 1 will turn it off.
Perform a functional simulation testing all possible inputs for your program. After verifying that your
program will work correctly, program the DE0 board with your VHDL program.
Upload the following files:
Your .qpf file
Your .vhd file
Your .qsf file
Your .vwf file
Solution
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port (
clk : in std_logic;
bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end test;
--\'a\' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
begin
process (clk,bcd)
BEGIN
if (clk\'event and clk=\'1\') then
case bcd is
when \"0000\"=> segment7 <=\"0000001\"; -- \'0\'
when \"0001\"=> segment7 <=\"1001111\"; -- \'1\'
when \"0010\"=> segment7 <=\"0010010\"; -- \'2\'
when \"0011\"=> segment7 <=\"0000110\"; -- \'3\'
when \"0100\"=> segment7 <=\"1001100\"; -- \'4\'
when \"0101\"=> segment7 <=\"0100100\"; -- \'5\'
when \"0110\"=> segment7 <=\"0100000\"; -- \'6\'
when \"0111\"=> segment7 <=\"0001111\"; -- \'7\'
when \"1000\"=> segment7 <=\"0000000\"; -- \'8\'
when \"1001\"=> segment7 <=\"0000100\"; -- \'9\'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <=\"1111111\";
end case;
end if;
end process;
end Behavioral;
