A32K8 RAM chip uses coincident decoding by splitting the int

A32K*8 RAM chip uses coincident decoding by splitting the internal decoder into row and column select assuming that the RAM cell arrat is square what is the size of each decoder and how many AND gates are required for decoding an address and detrmine the row and cloumn selection lines that are enabled when the input address is binary from chapter8 ,3p

Solution

1) size of each decoder is:

row decoder:

N=32K*8=2⁵ * 2¹⁰ * 2³=2¹⁸

square implies that each side of square has 2⁹ bits. the row decoder is 9 line to 512 line decoder.

column decoder:

The column decoder reference a 8 bit byte because a 32k* 8 RAM need to be created.

each side of square has 2⁹ bits.There fore column decoder:

2⁹= c * 2³

that\'s why c=2⁶  The column decoder is a 6 line to 64 line decoder.

2)AND gates are required for decoding an address:

Row decoder + column decoder = 2⁹ +2⁶ =64+ 512 =576

3) The row and cloumn selection lines that are enabled when the input address is binary from chapter8 ,3p:

chapter 8 3p problem has binary equivallent to (32,000)₁₀

(32,000)₁₀ =(7D00)₁₆=(111 1101 0000 0000)₂

row=(1 1111 0100)₂

column=(00 0000)₂

row=(500)₁₀

column=(0)₁₀