please explain each steps thank you Circle whether each chan

please explain each steps thank you

Circle whether each change will make something decrease (-), increase (+) or remain the same (=). The effects you will consider is the number of instructions in the program, the amount of cycles for each instruction (in a pipelined processor) and the amount of time for each cycle (seconds/cycle).

Solution

Instruction/program cycles/instruction seconds/cycle reducing the number of registers in ISA Increase(+): values Will more frequently be spilled to the stack, due to increasing number of loads and stores Increase(+): more loads followed by dependent instructions, will cause stalls, and likely be difficult to schedule around Decrease(-): fewer registers means shorter register file access time adding a branch delay slot Increase(+): Nops must be inserted when the branch delay slot cannot be usefully filled. Decrease()-: Some control hazards are eliminated; also additional NOPs execute quickly because they have no data hazards. No effect(=): doesn’t change pipeline Decrease: branch_kill signal is no longer needed merging the execute and mem stages Decrease(-): if the added instruction can replace a sequence of instructions. Increase(+): if implementing the instruction means adding or re-using stages. Increase(+): since more logic and thus longer critical path. changing the implementation from a microcoded CISC machine to RISC No effect(=): because the ISA is not changing, the binary does not change, and thus there is no change to Inst/ Program. Decrease(-): Microcoded machines take several clock cycles to execute an instruction, while the RISC pipeline should have a CPI near 1 (thanks to pipelining). No effect(=): the amount of work done in one pipeline stage and one microcode cycle are about the same. Increase: the RISC pipeline introduces longer control paths and adds bypasses, which are likely to be on the critical path.