QUESTION 5 10 points Design the instruction encoding for the

QUESTION 5. (10 points) Design the instruction encoding for the instruction variants below.

• Show the instruction format of each instruction variant

• Mention how many bits each field occupies

• Find each instruction size in bytes

• Decide whether a fixed-length or variable-length is suitable for this ISA

Add Reg, Reg, Reg

Add Reg, Reg, Const # constant of 10-bit or larger Load Reg, [Reg + Reg + const] # constant of 10-bit or larger

Load Reg, [Reg + Reg*d + const] # constant of 10-bit or larger

_ # d is the scale (1,2,4,8)

Store [Reg+const32], const32 # constants are 32-bit

The architecture supports 220 instructions that are encoded directly by the opcode. There are 16 general-purpose registers.

I1: Add Reg, Reg, Reg

I2: Add Reg, Reg, Reg

I3: Load Reg, [Reg+Reg+const]

I4: Load Reg, [Reg+Reg *d + const]

I5: Store [Reg + const 32], const32

Insrtuction format:

If the given instructions are three address instruction.

I1 = Register to Register

I2 = Register to Register

I3 = Register to Indexed Storage

I4 = Register to Storage

I5 = Storage Immediate

The number of bits occupied by each field:

Add R3, R1, R2 # 15 bits

Add R4, R1, data # 42 bits

Load R5, [R3 + R5 +data] # 47 bits

Load R6, [ R3 + R5 *d + data] # 47 bits

Store [R4 + data] data # 42 bits

data [ 32 bits]

which is 00000000000000001111111111111111