Consider a busbased multiprocessor system that uses writebac

Consider a bus-based multiprocessor system that uses write-back caches with a snoopy cache coherence protocol, which is an invalidate protocol with three states, exclusive, shared, and invalid. The following sequence of memory references is performed. For each one, indicate with Y or N whether it is a cache hit or miss, and whether it causes a bus transaction?

Reference P1: Read A P2: Read A P2: Write A P1: Read A P2: Read A P1: Read B P2: Write B P2: Write A P1: Read B P1: Write B Hit? Bus Transaction?

Solution

In write-back cache, data is written back to memory only when a cache block is about to be modified or there is a read miss. A bus transaction occurs only when a processor requests a block which is not updated in it\'s cache. Initially all the cache contain same data

	Hit	Bus Transaction
P1: Read A	Y	N
P2: Read A	Y	N
P2:Write A	Y	N
P1: Read A	N	Y	Fetch from cache of P2
P2: Read A	Y	N
P1:Read B	Y	N
P2: Write B	Y	N
P2: Write A	N	Y	Write miss. Write back to main memory
P1: Read B	N	Y	Fetch from cache of P2
P1: Write B	Y	Y	P2 should write back to main memory