I am trying to write a top level module for 4x1 mux circuit

I am trying to write a top level module for 4x1 mux circuit to implement the circuit on an Altera FPGA board. What I am having trouble is crating the top level module to implement the circuit on an Altera FPGA board. the top level has to have

a. Data input - switches 3:0

b. Select input - switches 5:4

c. need to show switch states on the red leds

d. and need to show the mux output on the HEX0 seven segment display. Values shown will either be 0 or 1.

Use concatenation to form the four bit signal required by the seven segment module.

assign {A, B, C, D} = { 3’b000, m}; where A, B, C, D are the 7 segment module inputs; m is the mux output.

Here is my code for 4X1 mux.

//4:1 mux
module mux1to4( m,A,B,C,D,a,b);
output m;
input a,b;//select
input A,B,C,D;

assign m = (~a&~b&A )|(~a&b&B )|(a&~b&C )|(a&b&D);

endmodule

Here is also my top level

module mux4to1_top(A,B,C,C,SW,s, LEDR, HEX0);

   input [3:0]SW;// toggle switches
   input [5:4]s;
   output [3:0] LEDR;
   output [6:0]HEX0;//7 segment display
   wire m;
   assign LEDR = SW;
   assign {A, B, C, D} = { 3’b000, m};
   mux1to4 inst0(SW[3:0],S[5:4],LEDR);
   //hex_7seg_bitwise inst1 (m,HEXO);

endmodule

Solution

Hello ,

I have made the changes to you code. It should run properly if you assign the pin correctly.

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/4:1 mux
module mux1to4( m,A,B,C,D,a,b);
output m;
input a,b;//select
input A,B,C,D;

assign m <= (~a&~b&A )|(~a&b&B )|(a&~b&C )|(a&b&D);

endmodule

module mux4to1_top(A,B,C,D,SW,s, LEDR, HEX0);

   input [3:0]SW;// toggle switches
    input [5:4]s;
    output [3:0] LEDR;
    output [6:0]HEX0;//7 segment display
    wire m;
    assign LEDR = SW;
    assign {A, B, C, D} = { 3’b000, m};
    mux1to4 inst0(m,SW[3:0],S[5:4],LEDR);
    //hex_7seg_bitwise inst1 (m,HEXO);

endmodule

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Please let me know in case of any issue