Consider this sequence of instructions Complete the above pi

Consider this sequence of instructions. Complete the above pipeline diagram, which shows the two instructions executing under ideal conditions, i.e., assuming no hazards exist. There is a data hazard between the add and s11 instructions. Is it a/an: load use data hazard; EX hazard; MEM data hazard; store word data hazard; or just an unnamed data hazard? Assuming the only wav w

Solution

2 Option (b) EX Data Hazard:

Notice that data hazards of this type (R-type instructions) occur
when one of the following four conditions is met:
– Those where one of the two ALU arguments is currently in the
EX/MEM i t EX/MEM register (d d i i t ti ) (dependency on previous instruction)
• EX/MEM.RegisterRd = ID/EX.RegisterRs,
• EX/MEM.RegisterRd = ID/EX.RegisterRt
– Those where one of the two ALU arguments is currently in the
MEM/WB register (dependency on instruction two ahead in pipeline).
• MEM/WB.RegisterRd = ID/EX.RegisterRs
• MEM/WB.RegisterRd = ID/EX.RegisterRt

Detecting Data Dependencies: Given two instructions, i and j (i occurs before j). • We say a dependence exists between i and j if j reads the result produced by i, and there is no instruction k which occurs between i and j and that produces the same result as i. • We call a data dependence a hazard when an instruction tries to read a register in stage 2 (ID) and this register will be written by a previous instruction that has not yet completed stage 5 (WB). • This is sometimes called a read-after-write hazard. • What kind of instructions can create data dependences? • Modern microprocessors have several ALUs, floating point units that take longer than integer units, etc which give rise to other kinds of data hazards.

Resolving Data Hazards: There are several options: •Build a hazard detection unit, which stalls the pipeline until the hazard has passed. It does this by inserting “bubbles” (essentially nops) in the pipeline. This isn’t a great idea. We’d like to avoid it, if possible. •Forwarding. Forward the result as an ALU source. •Software (static) scheduling. Leave it up to the compiler. It must schedule instructions to avoid hazards. Often it won’t be able to, so it will issue no-ops (an instruction that does nothing) instead. This is the cheapest (in terms of hardware) solution. •Hardware (dynamic) scheduling. Build special hardware that schedules instructions dynamiclly.