I have ASM chart and I need verilog design for FPGA Board I

I have ASM chart and I need verilog design for FPGA Board.

I put the link, you can use mouse\'s wheel for zoom in or out.

https://drive.google.com/file/d/0B75TQswkTit5bTJCRHU4TkNpUW0yb2lVcnBjOEcxWS01bE5B/view?usp=sharing

Solution

// waitForCoin, totalOfCoin, coinAmountValid, vending, giveLeftOverCoins are the states
// Decision is based on decision making blocks: coinInMachine, burritoSelected, enoughCoins, leftCoins
module asm_chart(input clk, input coinInMachine, input burritoSelected, input enoughCoins, input leftCoins);
reg [1:0] state, nextstate;
parameter [2:0] waitForCoin=0, totalOfCoin=1, coinAmountValid=2, vending = 3, giveLeftOverCoins = 4;
always @(posedge clk) // always block to update state
state <= nextstate;
always @(state or coinInMachine or burritoSelected or enoughCoins or leftCoins) // check the state in decision making block
begin
case(state)
waitForCoin: if(coinInMachine)
nextstate= totalOfCoin;
else
nextstate= waitForCoin;
totalOfCoin: if(burritoSelected)
begin
if(enoughCoins)
nextstate= vending;
else
nextstate= coinAmountValid;
end
else
nextstate= waitForCoin;
coinAmountValid:
nextstate= waitForCoin;
vending: if(leftCoins)
nextstate=giveLeftOverCoins;
else
nextstate= waitForCoin;
giveLeftOverCoins:
nextstate=waitForCoin;
default:
nextstate= waitForCoin;
endcase
end

endmodule