Analyze the clocked synchronous state machine show below Ass

Analyze the clocked synchronous state machine show below. Assume that unconnected or unshown inputs are wire appropriate to allow normal functionality. [For example, the clock is not shown (for clarity), but should be assumed to be present] Simplify all equations Input Equations D1 = D0 = Output Equation Z = Circle One Z is Mealy or Z is Moore This design is implemented with LS devices having the following characteristics: Comb. Gates propogation delay, input to output (min): 1 ns input to output (max): 2 ns DFF propogation delay, clock to output (min): 4 ns clock to output (min): 6ns input to output (min, max): infinity DFF setup time, data input before clock: 5ns DFF setup time, data input after clock: 3ns Calculate the timing parameters for the design. Prop, delay, clock to output (min): Prop, delay, input to output (max): Setup time, data input before clock: Hold time, data input after clock: Maximum clock rate:

Solution

a) Input equation:

D1=X.Q0

D0=x

b)

Z=Q1.Q0

c)Moore machine

Since the output depends upon only memory unit .

d)

4+1=5ns

e)proagation delay:

5ns