Your team is to design a single cycle machine that implement

Your team is to design a single cycle machine that implements the MIPS32 assembly instructions which have been described in the slides. You should use model the computer using a HDL behaviour of your choice (either Verilog or VHDL). This hardware description will be mapped to our FPGA boards and synthesized using Xilinx. In this homework problem, you are to design the ALU with the following module I/O. module ALU(input [7:0] a, b, input [3:0] ALUop, output reg [7:0] result, output reg zero_detect) ;

Solution

find the verilpg code as below:

module alu(a,b,ALUop,result,zero_detect);

input [7:0] a,b; // port a and b
output [7:0] result; // alu result
output zero_detect ; // zero output
input [3:0] ALUop ; // control for ALU
wire [7:0] result;

assign result = alu_out(a,b,ALUop);   
assign zero_detect = zero_flag(result) ;

function [7:0] alu_out;
input [7:0] a,b ;
input [3:0] ALUop ;
case ( ALUop )
4\'b0000: alu_out=a; // select data on port a
4\'b0001: alu_out=a+8\'b00000001 ; // increment data on port a
4\'b0010: alu_out=a-8\'b00000001 ; // decrement data on port a
4\'b0011: alu_out=a+b; // Addtion
4\'b0100: alu_out=a-b ; // Subtraction
4\'b0101: alu_out=a&b; // and operation
4\'b0110: alu_out=a|b; // or operation
4\'b0111: alu_out=a^b; // xor operation
4\'b1000: alu_out={b[6:0],1\'b0}; // shift data left
4\'b1001: alu_out={1\'b0,b[7:1]}; // shift data Right
4\'b1010: alu_out = ~b ; // complement
default : begin
alu_out=8\'bxxxxxxxx;
$display(\"Illegal ALUop detected!!\");
end
endcase
endfunction // end of function \"result\"

function zero_flag ;
input [7:0] z ;
begin
zero_flag = ^(z[0]|z[1]|z[2]|z[3]|z[4]|z[5]|z[6]|z[7]) ; // zero flag check for z
end
endfunction

endmodule