I am experimenting with VHDL In Altera Cyclone II on a DE2 a

Solution

components such as oneshot, colorROM, ps2, keyboard, VGA_SYNC and leddcd that were provided were not modified. VGA_top_level

library IEEE;

use IEEE.std_logic_

1164.all; entityVGA_top_level is port( CLOCK_50 : in std_logic;

RESET_N : in std_logic;

keyboard_clk, keyboard_data: in std_logic;

--VGA VGA_RED, VGA_GREEN, VGA_BLUE : out std_logic_vector(9 downto 0);

HORIZ_SYNC, VERT_SYNC, VGA_BLANK, VGA_CLK : out std_logic;

score_tank1_hex : out std_logic_vector(6 downto 0); score_tank2_hex : out std_logic_vector(6 downto 0);

--lcd res_led : in std_logic;

LCD_RS, LCD_E, LCD_ON, RESET_LED, SEC_LED : OUT STD_LOGIC; LCD_RW : BUFFER STD_LOGIC; DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) );

end entity VGA_top_level;

architecture structural of VGA_top_level is componentpixelGenerator is port( clk, ROM_clk, rst_n, video_on, eof : in std_logic;

pixel_row, pixel_column : in std_logic_vector(9 downto 0); keyboard_clk, keyboard_data : in std_logic; red_out, green_out, blue_out : out std_logic_vector(9 downto 0); score_tank1_hex : out std_logic_vector(6 downto 0); score_tank2_hex : out std_logic_vector(6 downto 0); tank1_win : buffer std_logic; tank2_win : buffer std_logic ); end component pixelGenerator; component VGA_SYNC is port( clock_50Mhz : in std_logic; horiz_sync_out, vert_sync_out, video_on, pixel_clock, eof : out std_logic; pixel_row, pixel_column : out std_logic_vector(9 downto 0) ); end component VGA_SYNC; component de2lcd IS PORT(reset, clk_50Mhz : IN STD_LOGIC; a_win, b_win : in std_logic; LCD_RS, LCD_E, LCD_ON, RESET_LED, SEC_LED : OUT STD_LOGIC; LCD_RW : BUFFER STD_LOGIC; DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END component de2lcd; --Signals for VGA sync signalpixel_row_int : std_logic_vector(9 downto 0); signalpixel_column_int : std_logic_vector(9 downto 0); signalvideo_on_int : std_logic; signalVGA_clk_int : std_logic; signaleof : std_logic; --lcd signal tank1_win, tank2_win : std_logic; begin -------------------------------------------------------------------------------------------- videoGen :pixelGenerator port map(CLOCK_50, VGA_clk_int, RESET_N, video_on_int, eof, pixel_row_int, pixel_column_int,keyboard_clk, keyboard_data,VGA_RED, VGA_GREEN, VGA_BLUE,score_tank1_hex,score_tank2_hex, tank1_win, tank2_win); -------------------------------------------------------------------------------------------- --This section should not be modified in your design. This section handles the VGA timing signals --and outputs the current row and column. You will need to redesign the pixelGenerator to choose --the color value to output based on the current position videoSync : VGA_SYNC port map(CLOCK_50, HORIZ_SYNC, VERT_SYNC, video_on_int, VGA_clk_int, eof, pixel_row_int, pixel_column_int); VGA_BLANK <= video_on_int; VGA_CLK <= VGA_clk_int; -------------------------------------------------------------------------------------------- lcd_map : de2lcd port map(res_led, cloCK_50, tank1_win, tank2_win, LCD_RS, LCD_E, LCD_ON, RESET_LED, SEC_LED, LCD_RW, DATA_BUS); end architecture structural; procedure.vhd libraryieee; use ieee.std_logic_1164.all; useieee.numeric_std.all; PACKAGE MY IS PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos: IN INTEGER;SIGNAL colorAddr:OUT STD_LOGIC_VECTOR(2 downto 0);SIGNAL DRAW: OUT STD_LOGIC); PROCEDURE SQ_B(SIGNAL Xcur_B,Ycur_B,Xpos_B,Ypos_B: IN INTEGER;SIGNAL colorAddr_B:OUT STD_LOGIC_VECTOR(2 downto 0);SIGNAL DRAW_B: OUT STD_LOGIC); END MY; PACKAGE BODY MY IS PROCEDURE SQ(SIGNAL Xcur,Ycur,Xpos,Ypos: IN INTEGER;SIGNAL colorAddr:OUT STD_LOGIC_VECTOR(2 downto 0);SIGNAL DRAW: OUT STD_LOGIC) IS BEGIN IF(Xcur>Xpos AND Xcur<(Xpos+50) AND Ycur>Ypos AND Ycur<(Ypos+50))THEN colorAddr<=\"111\"; DRAW<=\'1\'; ELSE DRAW<=\'0\'; END IF; END SQ; PROCEDURE SQ_B(SIGNAL Xcur_B,Ycur_B,Xpos_B,Ypos_B: IN INTEGER;SIGNAL colorAddr_B:OUT STD_LOGIC_VECTOR(2 downto 0);SIGNAL DRAW_B: OUT STD_LOGIC) IS BEGIN IF(Xcur_B>Xpos_B AND Xcur_B<(Xpos_B+15) AND Ycur_B>Ypos_B AND Ycur_B<(Ypos_B+15))THEN colorAddr_B<=\"000\"; DRAW_B<=\'1\'; ELSE DRAW_B<=\'0\'; END IF; END SQ_B; END MY;