15 Write a VHDL process to model a 4x2 encoder with register

15. Write a VHDL process to model a 4x2 encoder with registered output and reset.

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity encoder is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder;

architecture bhv of encoder is
begin

process(a)
begin
if (a=\"1000\") then
b <= \"00\";
elsif (a=\"0100\") then
b <= \"01\";
elsif (a=\"0010\") then
b <= \"10\";
elsif (a=\"0001\") then
b <= \"11\";
else
b <= \"XX\";
end if;
end process;

end bhv;