provide VHDL code for a 4bit multifunction register Write a

provide VHDL code for a 4-bit multifunction register

Write a behavioral VHDL code that implements a 4-bit multifunction register that does parallel load, shift right, shift left, and rotate right operations. Write a VHDL test bench to test the operations with at least one test vector per operation.

Solution

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-- Company:
-- Engineer:
--
-- Create Date: 22:29:11 10/11/2016
-- Design Name:
-- Module Name: multifunctionshift - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity multifunctionshift is
Port ( D : in STD_LOGIC_VECTOR (3 downto 0);
CLK, RST : in STD_LOGIC;
SIR, SIL : in STD_LOGIC;
S :in STD_LOGIC_VECTOR (1 downto 0);
Q : out STD_LOGIC_VECTOR (3 downto 0));
end multifunctionshift;

architecture Behavioral of multifunctionshift is
begin

process(CLK, RST) is
variable REG : std_logic_vector(3 downto 0);
begin
if (RST = \'0\') then
REG := (others => \'0\');
elsif rising_edge(clk) then
case S is
when \"00\"=>REG := D;
when \"01\" =>REG := SIR & REG(3 downto 1);
when \"10\" =>REG := REG(2 downto 0) & SIL;
when others=>REG:= REG(0)& REG(3 downto 1);
end case;
end if;
Q <= REG;
end process;
end Behavioral;