Need verilog code for Design and build a 4bits synchronous u

Need verilog code for: Design and build a 4-bits synchronous up/down counter with an enable. This counter has three inputs Clock, ENABLE, and UP/DOWN’ and four outputs O3 (MSB),O2,O1, and O0 (LSB). The table below defines the circuit behavior:

ENABLE UP/DOWN\' Function 0 X Stop counting 0 Count down: 15,14,...,1,0,15,14, Count up: 0,1,...,14,15,0,1

Solution

https://www.google.co.in/url?sa=t&source=web&rct=j&url=http://www.allaboutcircuits.com/textbook/digital/chpt-11/synchronous-counters/&ved=0ahUKEwjB7IuZ8c3NAhUJNI8KHVnhAUgQFghOMA0&usg=AFQjCNEuRipSTeHcOf2clZzlfTE21SCe-Q&sig2=e4bQauGsNY9WJIztJYb1UQ