Write a VHDL entityarchitecture pair for calculating the fol

Write a VHDL entity-architecture pair for calculating the following logic functions in IEEE 1164 logic: y_1 = ab + c + d +abde y_2 = y_1 + abcd

Solution

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity design is
port( a, b, c, d, e: in std_logic;
       y1, y2: out std_logic;
     );
end design;
architecture synthesis of design is
begin

y1 <= (a AND b) OR c OR d OR (NOT a AND b AND c AND d);
y2 <= y1 OR (a AND b AND c AND d);

end synthesis