Solve and complete parts 1 and 2 Part 1 is a truth table and

Solve and complete parts 1 and 2.

Part 1 is a truth table and veilog code.

Part 2 is just verilog code.

Part 1 (HEX to SSD) A Hexadecimal-to-seven-segment decoder is a combinational circuit that converts a hexadecimal digit to arn appropriate code for the selection of segments in an indicator used to display the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding LEDs in the display, as shown in figure below. The numeric display chosen to represent the hexadecimal digit is shown as well. (a) Segment designation (b) Numerical designation for display 89A6E8BB Write the truth table relating the four binary inputs to the 7 LED outputs of the BCD-to-seven-segment decoder. DO NOT use K-Maps. There\'s no need for logic expressions. Draft the Verilog code using behavioral modeling. Use a Case Statement relating the binary number input to it seven-segment representation. Part 2 (SHIFT LEFT REGISTER) Draft the Verilog code for a 4-bit shift left register with Positive-Edge Clock, Serial In, and Serial Out. Don\'t forget to properly define the input and sum registers. Hint:

Solution

1)

Verilog Code:

module bcd2seven(bcd,abcdefg);

input [3:0] DCBA;
output [6:0] abcdefg;
reg [6:0] abcdefg;

always @(DCBA)
begin
case (DCBA) //case statement
0 : abcdefg = 7\'b1111110;
1 : abcdefg = 7\'b0110000;
2 : abcdefg = 7\'b1101101;
3 : abcdefg = 7\'b1111001;
4 : abcdefg = 7\'b0110011;
5 : abcdefg = 7\'b1011011;
6 : abcdefg = 7\'b1011111;
7 : abcdefg = 7\'b1110000;
8 : abcdefg = 7\'b1111111;
9 : abcdefg = 7\'b1111011;
  
  
endcase
end
  
endmodule

truth table:

D	C	B	A	abcdefg
0	0	0	0	1111110
0	0	0	1	0110000
0	0	1	0	1101101
0	0	1	1	1111001
0	1	0	0	0110011
0	1	0	1	1011011
0	1	1	0	1011111
0	1	1	1	1110000
1	0	0	0	1111111
1	0	0	1	1111011