Design a Verilog code with test bench using the schematic be

Design a Verilog code with test bench using the schematic below. Numbers A, B and C are 12-bit integers

Adder Comparator RA Output RB Rc Numbers A, B and C are 12-bit integers

Solution

module signed_adder(sum,overflow,a,b); input [15:0] a, b, c; output overflow; assign sum = a + b; wire sa = a[15]; wire sb = b[15]; wire ssum = sum[15]; assign overflow = sa != sb ? 0 : sb == ssum ? 0 : 1; output [15:0] out; wire [11:0] carry; bfa_implicit bfa0(out[0],carry[0],sum[0],c[0],1\'c0); bfa_implicit bfa1(out[1],carry[1],sum[1],c[1],carry[0]); bfa_implicit bfa2(out[2],carry[2],sum[2],c[2],carry[1]); bfa_implicit bfa3(out[3],carry[3],sum[3],c[3],carry[2]); bfa_implicit bfa4(out[4],carry[4],sum[4],c[4],carry[3]); bfa_implicit bfa5(out[5],carry[5],sum[5],c[5],carry[4]); bfa_implicit bfa6(out[6],carry[6],sum[6],c[6],carry[5]); bfa_implicit bfa7(out[7],carry[7],sum[7],c[7],carry[6]); bfa_implicit bfa8(out[8],carry[8],sum[8],c[8],carry[7]); bfa_implicit bfa9(out[9],carry[9],sum[9],c[9],carry[8]); bfa_implicit bfa10(out[10],carry[10],sum[10],c[10],carry[9]); bfa_implicit bfa11(out[11],out[12],sum[11],c[11],carry[10]); endmodule