KINDLY WRITE THE VDHL CODE USE XILINX Write VHDL code for th

KINDLY WRITE THE VDHL CODE USE XILINX

Write VHDL code for the LFSR circuit given in Fig 1. Use the sample entity statement shown in Fig 2. Use the testbench code given with assignment to test your VHDL code. (Note: For the D-flip-flop, make output node, Q goes to logic \'1\' or \"high\" when reset is at logic \"1\" or \"high\" and also if the name of the ports in the entity is different than the VHDL code shown in Fig 2, the testbench will not work). library IEEE; use IEEE.STD_LOGIC_1164. ALL; entity LFSR is Port (Clk, Reset: in STD_LOGIC; LFSR_out: out STD_LOGIC_VECTOR (3 downto 0)); end LFSR; architecture Behavioral of LFSR is begin end Behavioral;

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LFSR is
Port ( clk,Reset : in STD_LOGIC;
LFSR_out : out STD_LOGIC_VECTOR (3 downto 0));
end LFSR;

architecture Behavioral of LFSR is
component DFF
Port ( D,Clock,R : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
signal L:STD_LOGIC_VECTOR (3 downto 0);
signal X:STD_LOGIC;
begin
d0:DFF port map(L(1),clk,Reset,L(0));
d1:DFF port map(L(2),clk,Reset,L(1));
d2:DFF port map(L(3),clk,Reset,L(2));
X<=L(0) xor L(1);
d3:DFF port map(X,clk,Reset,L(3));

end Behavioral;

%%VHDL code for D flipflop:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity DFF is
Port ( D,Clock,R : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF;

architecture Behavioral of DFF is

begin

process(Clock,R)
begin
if (R=\'1\') then
Q<=\'1\';
elsif (Clock\'event and Clock=\'1\') then
Q<=D;
end if;
end process;

end Behavioral;