For a particular inverter design using a power supply Add wi

For a particular inverter design using a power supply Add with Val = 0.3Vdd, Vow = 0.5Vdd, V_iI = 0.5Vdd, and Via = 0.4Vdd. In order to maintain noise margins of at least 0.2V for both noise margin high (logical 1) and noise margin low (logical 0), what are the requirements of Veda? (20%)

Solution

Noise margin high=V_OH-V_IH=0.5V_DD-0.4V_DD=0.1V_DD

Noise margin low=VIL-VOL=0.5V_DD-0.3V_DD=0.2V_DD

From the above two equations, V_DD shold be atleast 2 volts to maintain maintain noise margin of atleast 0.2 volts.

So V_DD shold be greater than or equal to 2 volts