Please help me fix my VHDL program I get these errors when I

Please help me fix my VHDL program. I get these errors when I compile it. I am not suire what it is wanting me to change.

Error (10500): VHDL syntax error at homewk4_9.vhd(18) near text \"=\"; expecting \"(\", or \"\'\", or \".\"
Error (10500): VHDL syntax error at homewk4_9.vhd(21) near text \"PROCESS\"; expecting \"if\"

Here is the file;

ENTITY homewk4_9 IS
PORT(
CLOCK       :IN BIT;
CLR       :IN BIT;
QOUT       :BUFFER INTEGER RANGE 0 TO 7);
END homewk4_9;
ARCHITECTURE behavior OF homewk4_9 IS
BEGIN
PROCESS(CLOCK, CLR)
BEGIN
IF(CLR = \'0\') THEN
QOUT <= 0;
ELSE IF(CLOCK\'EVENT AND CLOCK = \'1\') THEN
IF QOUT = 0 THEN QOUT <= 1;
ELSE IF QOUT = 1 THEN QOUT <= 2;
ELSE IF QOUT = 2 THEN QOUT <= 6;
ELSE IF QOUT = 6 THEN QOUT <= 7;
ELSE QOUT = 7 THEN QOUT <= 0;
END IF;
END IF;
END PROCESS;
END behavior;

Solution

ENTITY homewk4_9 IS
PORT(
CLOCK       :IN BIT;
CLR       :IN BIT;
QOUT       :BUFFER INTEGER RANGE 0 TO 7);
END homewk4_9;
ARCHITECTURE behavior OF homewk4_9 IS
BEGIN
PROCESS(CLOCK, CLR)
BEGIN
IF(CLR = \'0\') THEN
QOUT <= \'0\'; ---------here is the error.you have to put \' \' after declaration
ELSIF(CLOCK\'EVENT AND CLOCK = \'1\') THEN ---------the second error is here.if you put ELSE IF you have to end the else if loop.otherwisw put ELSIF.need not end the if loop
IF QOUT = \'0\' THEN QOUT <= \'1\';
ELSIF QOUT = \'1\' THEN QOUT <= \'2\';
ELSIF QOUT = \'2\' THEN QOUT <= \'6\';
ELSIF QOUT = \'6\' THEN QOUT <= \'7\';
ELSE QOUT = \'7\' THEN QOUT <= \'0\';
END IF;
END IF;
END PROCESS;
END behavior;