Write complete VHDL code that will generate a fixed number o

Write complete VHDL code that will generate a fixed number of clock cycles using for loop by including a variable num_cycles in your design as generic parameter. Simulate your design for correct functionality.

Solution

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test_tb IS END test_tb; ARCHITECTURE behavior OF test_tb IS COMPONENT test PORT(clk : IN std_logic;) END COMPONENT; signal clk : std_logic := \'0\'; constant clk_period : time := 1 ns; BEGIN uut: test PORT MAP (clk => clk); -- Clock process definitions( clock with 50% duty cycle is generated here. clk_process :process begin clk <= \'0\'; wait for clk_period/2; --for 0.5 ns signal is \'0\'. clk <= \'1\'; wait for clk_period/2; --for next 0.5 ns signal is \'1\'. end process; END;