9ATDAT Lf z mes mmmm mmmm7 DAT Z st DAT ZED o CLK means no

-9_ATDAT- Lf- z + mes mmmm mmmm---7 DAT Z st DAT ZED o CLK means \"no connection\" . Leeeeeeen Q0 D 5 a ar

Solution

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--This is a D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clk).
--Note that the reset input has the highest priority,Set being the next highest
--priority and clock enable having the lowest priority.
entity sync is
port(
B,ZED : out std_logic; --system output
CLK :in std_logic; -- Clock input
CLR :in std_logic; -- Synchronous reset input
DAT :in std_logic; -- Data input
  
);
end sync;
architecture Behavioral of sync is --architecture of the circuit.
signal A,DA,DB,QA,QB,Z:std_logic;
begin --\"begin\" statement for architecture.
process(CLK) --process with sensitivity list.
begin --\"begin\" statment for the process.
DA<=DAT xor B;
DB<=A;
Z<=(not B)xor(A xor DAT);
if (CLR = \'1\') then
QA <= \'0\';QB<=\'0\';
elseif ( rising_edge(CLK) ) then --This makes the process synchronous(with clock)


QA <= DA;
QB<=DB;   
end if;
  
end process; --end of process statement.
end Behavioral;