1 Write the sequence of gates in the longest and shortest pa

1)

Write the sequence of gates in the longest and shortest paths. If there are multiple answers, list at least two answers. (e.g., A:NAND?F:NAND?H:NOR).

Suppose there is no clock skew. What is the maximum clock frequency of this circuit?

2)

Question 5. Maximum operating frequency For the following circuit, the timing characteristics of the components are summarized below: . Flip-flop pcq clock-to-Q minimum delay (contamination delay) t-25 ps, data setup time t- 30 ps, data hold time thold 20 ps ccq setup » Logic gate: NAND propagation delay NANDp NOR propagation delay thoRod NAND propagation delay tNANDpd 25 ps, N ,-20 ps. NOR contamination delay tNORd-10 ps ,-25 ps. NAND contamination delay tNANDod-15 ps. NORp A:NAND F:NAND H:NOR D:NOR B:NAND J:NAND I:NOR E: NOR G:NAND C:NAND CLK CLK

Solution

1)

A:NAND D:NOR H:NOR J:NAND

B:NAND E:NOR I:NOR J:NAND

A:NAND F:NAND

C:NAND G:NAND

2)

Taking the longest path...

T_C = t_pcq + 2*t_NANDpd + 2*t_NORpd + t_setup

T_C = 40 ps + 50 ps + 40 ps + 30 ps

T_C = 160 ps

Max. Frequency = (1 / T_c) = 6.25 GHz