Two students were debating how to classify superscalar opera

Two students were debating how to classify superscalar operation versus the use of VLIW instructions. The debate was over which of these is an organizational feature and which is an architectural feature. Indicate which point of view you would support and explain why.

Solution

A superscalar processor is a CPU that implements a form of parallelism calledinstruction-level parallelism within a single processor. It therefore allows for morethroughput (the number of instructions that can be executed in a unit of time) than would otherwise be possible at a givenclock rate. A superscalar processor can execute more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to different execution units on the processor. Each execution unit is not a separate processor (or a core if the processor is a multi-core processor), but an execution resource within a single CPU such as an arithmetic logic unit.

In Flynn\'s taxonomy, a single-core superscalar processor is classified as anSISD processor (Single Instruction stream, Single Data stream), though many superscalar processors support short vector operations and so could be classified as SIMD (Single Instruction stream, Multiple Data streams). A multi-core superscalar processor is classified as an MIMD processor (Multiple Instruction streams, Multiple Data streams).

While a superscalar CPU is typically alsopipelined, pipelining and superscalar execution are considered different performance enhancement techniques. The former executes multiple instructions in the same execution unit in parallel by dividing the execution unit into different phases, whereas the latter executes multiple instructions in parallel by using multiple execution units.

The superscalar technique is traditionally associated with several identifying characteristics (within a given CPU):

Instructions are issued from a sequential instruction stream
The CPU dynamically checks for data dependencies between instructions at run time (versus software checking at compile time)
The CPU can execute multiple instructions per clock cycle