The shift register that would be used to delay serial data b

The shift register that would be used to delay serial data by 4 clock periods is

Solution

Option (a)- serial in serial out shift register.

The input to this register is given in serial fashion i.e. one bit after the other through a single data line and the output is also collected serially. The data can be shifted only left or shifted only right. Hence it is called Serial in Serial out shift register or a SISO shift register.

For one clock pulse it data will be shifted right by one position so if we give data at msb it takes four clock cycles to reach LSB where we take output. Hence it is used to delay serial data by four clock pulses.

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