Create a digital debounce The debounce is timing based and s

Create a digital debounce. The debounce is timing based, and should only acknowledge pulses greater than a set period. To make it easier to demonstrate in this lab, set the period to 1s. The input should be BTN 0, output should be LED 0. LED0 should only turn on if BTN 0 has be high for 1s and should not turn o unless BTN 0 has been released for more than 1s.

(i) Schematic or Verilog HDL code of the circuit

(ii) Constraint file

(iii) Demonstrate the working implementation

Solution

Digital Switch Debounce: entity SwitchDebouncer is generic (CLK_FREQ : positive; NUM_SWITCHES : positive); port ( clk : in std_logic; reset : in std_logic; switchesIn : in std_logic_vector(NUM_SWITCHES-1 downto 0); switchesOut : out std_logic_vector(NUM_SWITCHES-1 downto 0)); end SwitchDebouncer;