VHDL structural homework need vhdl code for an 8 bit divider

VHDL structural homework need vhdl code for an 8 bit divider that takes in 2 8bit signals A and B and produces an 8 bit output RESULT that is equals to (A / B).

this divider must be asynchronous and implemented on a structural level.

DO NOT IMPLEMENT THE BEHAVIORAL 8BIT DIVIDER.

NOTE: THE DIVIDER MUST BE ASYNCHRONOUS --> MEANING NO CLOCKS

please explain how it works aswell *** <=== its very important that you explain the code ****

please type down the code so its readable,

thanks alot

Solution

VHDL structural homework need vhdl code for an 8 bit divider that takes in 2 8bit signals A and B and produces an 8 bit output RESULT that is equals to (A / B). this divider must be asynchronous and implemented on a structural level.

function divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
variable a1 : unsigned(a\'length-1 downto 0):=a;
variable b1 : unsigned(b\'length-1 downto 0):=b;
variable p1 : unsigned(b\'length downto 0):= (others => \'0\');
variable i : integer:=0;

begin
for i in 0 to b\'length-1 loop
p1(b\'length-1 downto 1) := p1(b\'length-2 downto 0);
p1(0) := a1(a\'length-1);
a1(a\'length-1 downto 1) := a1(a\'length-2 downto 0);
p1 := p1-b1;
if(p1(b\'length-1) =\'1\') then
a1(0) :=\'0\';
p1 := p1+b1;
else
a1(0) :=\'1\';
end if;
end loop;
return a1;

end divide;

The function can be used as follows in your main module:
--An example of how to use the function.
signal a : unsigned(7 downto 0) :=\"10011100\";
signal b : unsigned(7 downto 0) :=\"00001010\";
signal c : unsigned(7 downto 0) :=(others => \'0\');
c <= divide ( a , b ); --function is \"called\" here.

For using the function you have to copy the code snippet between the green lines and put it in a package.The libraries I have used are given below:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all; -- for UNSIGNED