When do page faults occur Describe the actions taken by the

When do page faults occur? Describe the actions taken by the operating system when a page fault occurs. A certain computer provides its users with a virtual-memory space of 2^32 bytes. The computer has 2^18 bytes of physical memory. The virtual memory is implemented by paging with the page size as 4096 bytes. A user process generates the logical address 11123456 in Hexadecimal. Explain how the system establishes the corresponding physical location. When virtual memory is implemented in a computing system, there are certain costs associated with the technique, and certain benefits. List the costs and the benefits. Consider the following page reference string: 1, 2, 3, 4, 2, 1, 5, 6, 2, 1, 2, 3, 7, 6, 3, 2, 1, 2, 3, 6 How many page faults would occur for the following page replacement algorithms, assuming one, two, three, four and five page frames? Remember that all page frames arc initially empty, indicating that your first unique pages will all cost one page fault each. LRU replacement FIFO replacement Optimal replacement

Solution

1. pagefault occur while invalid page accessing can be done only. that is, it can be done if an access to a page that has not been brought in to main memory takes place.Actually the page access can be verified in memory by operating system, then its aborting the program if that is invalid access. if that is valid access then I/O requested to read the required page into the free frame. And upon the completion of I/O, the process table and the page table are updated and the instruction can be restarted.

2.Virtual address of binary form: 0001 0001 0010 0011 0100 0101 0110
since page size can be 2^12 and the page table size can be 2^20. so, the low-order 12 bits (0100 0101 0110) can be used for displacement in the page. while remaining 20 bits (0001 0001 0001 0010 0011) can be used for displacement in the page table.hence the offset bits concatenating with resulting page number to form final address.

3. - The costs can be hardware and lesser access time.

- And benefits are, Good utilization of memory and larger logical address space more than physical address space.

4. Frame 1:

LRU : 20 FIFO : 20 Optimal : 20

Frame 2:

LRU : 18 FIFO : 18 Optimal : 15

Frame 3:

LRU : 15 FIFO : 16 Optimal : 11

Frame 4:

LRU : 10 FIFO : 14 Optimal : 8

Frame 5:

LRU : 8 FIFO : 10 Optimal : 7

Frame 6:

LRU : 7 FIFO : 10 Optimal : 7

Frame 7:

LRU : 7 FIFO : 7 Optimal : 7