For A CMOS inverter with pMOS load PU PullUp element and nMO

For A CMOS inverter with pMOS load (PU= Pull-Up element) and nMOS driver (PD= Pull-Down element) with: VTn = 0.8 V, VTp = -0.7 V, (W/L)P = 4/1, (W/L)n = 2/1, VDD =3.9V,andn =p =1.5x10-5A/V2:

a- SketchtheVTCfortheCMOSinverterandidentifytheregionsof operation

b- Sketch the VTC and identify the regions of operation.

c- i- At slope of -1 (dVout/dVin = -1) of the VTC determine VinL|max, and

VOH|min

ii- At the other corner with slope of -1 for the VTC determine

VinH|min, and VOL|max.

iii- Calculate the High and the LOW Noise Margins (NMH and NML)

iv- As the Designer in charge, what would you do to the transistor

characteristics to improve the Noise Margins?

Solution

in order to increase the noise margins the compatible volatges are taken for proper operation of circuit