A 6bit carryripple adder built using 5 fulladders and 1 half

A 6-bit carry-ripple adder built using 5 full-adders and 1 half-adder to add two 6-bit numbers has a delay of ____ nanosecond(s), if each full-adder has a delay of 8 nanoseconds, the half adder has a delay of 4 nanoseconds, and if each wire connecting the output co of one adder to the input ci of the next adder has 2 nanoseconds delay. Assume no delay for the other wires.
Note: Answer with a number.

Solution

54 nanoseconds.